DMP4025LSD-13 >
DMP4025LSD-13
Diodes Incorporated
MOSFET 2P-CH 40V 6.9A 8SO
10238 Pcs New Original In Stock
Mosfet Array 40V 6.9A 1.8W Surface Mount 8-SO
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DMP4025LSD-13 Diodes Incorporated
5.0 / 5.0 - (493 Ratings)

DMP4025LSD-13

Product Overview

12884312

DiGi Electronics Part Number

DMP4025LSD-13-DG
DMP4025LSD-13

Description

MOSFET 2P-CH 40V 6.9A 8SO

Inventory

10238 Pcs New Original In Stock
Mosfet Array 40V 6.9A 1.8W Surface Mount 8-SO
Quantity
Minimum 1

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In Stock (All prices are in USD)
  • QTY Target Price Total Price
  • 1 1.1295 1.1295
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DMP4025LSD-13 Technical Specifications

Category Transistors, FETs, MOSFETs, FET, MOSFET Arrays

Manufacturer Diodes Incorporated

Packaging Cut Tape (CT) & Digi-Reel®

Series -

Product Status Active

Technology MOSFET (Metal Oxide)

Configuration 2 P-Channel (Dual)

FET Feature Logic Level Gate

Drain to Source Voltage (Vdss) 40V

Current - Continuous Drain (Id) @ 25°C 6.9A

Rds On (Max) @ Id, Vgs 25mOhm @ 3A, 10V

Vgs(th) (Max) @ Id 1.8V @ 250µA

Gate Charge (Qg) (Max) @ Vgs 33.7nC @ 10V

Input Capacitance (Ciss) (Max) @ Vds 1640pF @ 20V

Power - Max 1.8W

Operating Temperature -55°C ~ 150°C (TJ)

Mounting Type Surface Mount

Package / Case 8-SOIC (0.154", 3.90mm Width)

Supplier Device Package 8-SO

Base Product Number DMP4025

Datasheet & Documents

HTML Datasheet

DMP4025LSD-13-DG

Environmental & Export Classification

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 1 (Unlimited)
REACH Status REACH Unaffected
ECCN EAR99
HTSUS 8541.29.0095

Additional Information

Other Names
DMP4025LSD-13DITR
DMP4025LSD13
DMP4025LSD-13DICT
DMP4025LSD-13DIDKR
Standard Package
2,500

Alternative Parts

PART NUMBER
MANUFACTURER
QUANTITY AVAILABLE
DiGi PART NUMBER
UNIT PRICE
SUBSTITUTE TYPE
IRF7328TRPBF
Infineon Technologies
16837
IRF7328TRPBF-DG
0.0113
MFR Recommended
IRF9362PBF
Infineon Technologies
16335
IRF9362PBF-DG
0.0113
MFR Recommended

Reviews

5.0/5.0-(Show up to 5 Ratings)
Serena***éleste
December 02, 2025
5.0
Ils assurent une logistique fluide et une communication claire sur leur politique tarifaire.
Lueur***inale
December 02, 2025
5.0
Le suivi des livraisons est précis et rassurant à chaque étape.
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December 02, 2025
5.0
DiGi Electronics me propose une expérience d’achat agréable, efficace et économique.
み***ん
December 02, 2025
5.0
注文の調整にも柔軟に対応してくれて、大変満足しています。
Fire***Glow
December 02, 2025
5.0
I enjoy shopping at DiGi Electronics because of their welcoming team and cost-effective prices.
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Frequently Asked Questions (FAQ)

What are the key design risks when using the DMP4025LSD-13 in a high-temperature environment near its maximum junction temperature of 150°C?

When using the DMP4025LSD-13 in environments approaching 150°C, thermal runaway is a primary risk due to increased Rds(on) at elevated temperatures. Even though the device is rated for 1.8W dissipation, ensure adequate PCB copper area (preferably with thermal vias) to conduct heat away, especially since it's a surface-mount 8-SO package. Simulate worst-case power scenarios considering idle and peak loads. Also verify that nearby components don’t create localized hot spots on the board. Use thermal derating curves to confirm safe operating area (SOA) compliance under sustained load conditions to avoid long-term reliability degradation.

How does the DMP4025LSD-13 compare to the SI7425DN as a P-channel dual MOSFET replacement in a 12V power switch application?

The DMP4025LSD-13 can serve as a viable alternative to the SI7425DN in 12V power switching, but with trade-offs. While both are dual P-channel logic-level MOSFETs in 8-SOIC packages, the DMP4025LSD-13 has a slightly higher Rds(on) of 25mΩ vs. SI7425DN’s 17mΩ at 10V Vgs, potentially increasing conduction losses. However, the DMP4025LSD-13 offers superior gate charge (33.7nC vs ~45nC) enabling faster switching and lower drive power. Check that your gate driver can pull up to at least 10V for full enhancement; at 3.3V logic, performance will degrade. Always verify current sharing and thermal coupling in dual configurations.

What PCB layout considerations are critical when integrating the DMP4025LSD-13 to minimize thermal and electrical stress?

For the DMP4025LSD-13, optimize PCB layout by maximizing copper connected to drain pads for heat dissipation—use at least 1 in² of 2oz copper with multiple thermal vias to inner ground planes. Keep gate traces short and routed away from high-current paths to prevent ringing and accidental turn-on due to capacitive coupling. Include a small gate resistor (5–10Ω) if switching inductive loads. Since it’s a dual P-channel array, avoid asymmetric source routing that could imbalance current sharing. Confirm via current capacity if high pulsed loads (e.g. motor startup) exceed 6.9A momentarily.

Can the DMP4025LSD-13 reliably replace aging IRF9Z24P devices in an existing 24V industrial control board?

Replacing IRF9Z24P with the DMP4025LSD-13 requires caution: although both are P-channel MOSFETs, the DMP4025LSD-13 is a dual 40V, 6.9A device in a surface-mount 8-SO package, whereas the IRF9Z24P is a single through-hole 55V device with higher current capability. The DMP4025LSD-13 is pin-compatible in function but not pin-to-pin; redesign is needed for SMT layout. Confirm that 40V Vdss suffices with margin over 24V nominal (including transients). Also validate that logic-level gate drive (≤2.5V threshold) aligns with your controller. Evaluate surge current handling and long-term reliability under industrial temperature swings.

What causes unexpected turn-on in DMP4025LSD-13 when used in motor control circuits, and how can it be prevented?

Unexpected turn-on in the DMP4025LSD-13 during motor control stems from dv/dt-induced gate coupling through Cgd (Miller effect), especially during fast voltage transients. Since the device has a logic-level gate and low Vgs(th), even small coupled voltages can bias the gate above threshold. To mitigate: add a gate-to-source resistor (10kΩ–100kΩ) to shunt displacement currents, use negative turn-off bias if feasible, and minimize parasitic trace inductance. Consider adding a small ceramic capacitor (1nF) between gate and source locally. Also verify that your driver has low impedance in the 'off' state to clamp the gate reliably under noisy conditions.

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